1. Field of the Invention
The present invention relates to a semiconductor memory device and a test method therefor, and more particularly, to a static random access memory (SRAM) and a test method therefor.
2. Description of Related Art
The recent miniaturization of static random access memories (SRAMs) has made it more difficult to secure their operation margin. As disclosed in Japanese Unexamined Patent Application Publication No. 2007-102902 and Published Japanese Translation of PCT International Publication for Patent Application, No. 2008-522334 (PCT Application WO 2006/056902), the operation margin of SRAMs is generally evaluated using static noise margin (SNM). In contrast to the SNM, dynamic noise margin (DNM) is known as an operation margin reflecting more actual operations.
Incidentally, in view of high speed operations and an improvement in the resistance of SRAMs to noise, the number of memory cells, i.e., the number of rows provided for each bit line pair tends to decrease. At present, it is considered that the number of rows is suitably in the range of about 8 to 32.
As a related art of the present invention, Japanese Unexamined Patent Application Publication No. 10-308100 discloses a method for testing an operation margin in a dynamic random access memory (DRAM). In addition, Japanese Unexamined Patent Application Publication No. 11-353898 discloses a method for testing an operation margin in a ferroelectric random access memory (FRAM).
Referring now to FIG. 12 which is a graph illustrating a change in noise margin with respect to the number of rows of memory cells of a 40 nm SRAM. The horizontal axis represents, in units of bits, the number of memory cells, i.e., row cells connected to each bit line pair. The longitudinal axis represents, in units of volt (V), a minimum operating voltage (VDDmin) for a memory cell serving as an index of a noise margin. A voltage equal to or higher than VDDmin is required to retain data.
Specifically, the SNM and DNM at six points where the number of rows=8, 16, 32, 64, 128, and 256 bits are plotted. As shown in FIG. 12, the SNM which is a static evaluation value is constant with respect to the number of rows. Meanwhile, the DNM is a dynamic evaluation value which rapidly decreases as the number of rows decreases, resulting in an increase in deviation from the SNM.